The disclosed embodiments of the present invention relate to adjusting a data path between two circuit components, and more particularly, to a reconfigurable circuit block supporting different interconnection configurations for a rate-conversion circuit and a processing circuit and a related method thereof.
In a conventional signal processing system, some circuit blocks may be configured to operate at clock frequencies each derived from a first reference clock source, and some blocks may be configured to operate at clock frequencies each derived from a second reference clock source, where a second reference clock provided by the second reference clock source is asynchronous with a first reference clock provided by the first reference clock source (e.g., one of the first reference clock frequency and the second reference clock frequency is not an integer multiple of the other of the first reference clock frequency and the second reference clock frequency). Therefore, it is essential to include a sampling rate converter in the conventional signal processing system to translate one digital signal sampled at one sampling rate to another digital signal sampled at another sampling rate. However, the arrangement of circuit blocks before the sampling rate converter and circuit blocks after the sampling rate converter may affect the performance of the conventional signal processing system under different scenarios.
Thus, there is a need for a reconfigurable circuit design which is capable of properly changing the arrangement of circuit blocks before the sampling rate converter and circuit blocks after the sampling rate converter to make the signal processing system have optimum performance for different scenarios.